Each new generation of semiconductors scales down the geometric dimensions of MOSFETs in CMOS circuits for improved speed and density. To maintain geometric similitude, all dimensions, such as MOSFET channel length, channel width, gate dielectric, junction depth, salicide thickness, well depth and epitaxial (epi) depth, are scaled by a constant parameter. To insure MOSFET reliability, the electric fields in the MOSFET are not scaled.
Electrical performance and power capabilities are also influenced as MOSFETs are scaled. Dimensional scaling decreases the MOSFET current and power dissipation. Scaling also leads to faster transistor speeds. Under scaling constraints, gate and drain voltages are scaled while well, epi and source/drain doping concentrations are scaled. In an ideal formulation, the sheet resistance of the source/drain, well and epitaxial scales as unity.
As CMOS technology is highly scaled, the vertical dimensions of the well and epitaxy as quickly as the lateral dimensions. Epi thickness and n-well implants may have to be maintained with scaling to allow room for retrograde well implants, etc., in order to maintain MOSFET device performance and other design criteria. Without proper scaling of the epitaxy and well implants, latchup immunity will decrease with technology scaling.
The scaling of the well and epitaxial region has an influence on CMOS latchup immunity, electrostatic discharge (ESD) protection, well sheet resistance and capacitance, noise immunity, soft error rate sensitivity, MOSFET snapback, MOSFET capacitance, diode series resistance, and other device design parametrics. Epitaxial layer thickness for a trench DRAM cell process is driven by denuded zone requirements, hot process, and n-well compensation effects. The epitaxial thickness is constrained by trench storage node capacitance, n-well-to-substrate capacitance, and trench gate-induced diode leakage (TGIDL) current mechanism requirements. The epitaxial optimization is followed by retrograde n-well optimization, both of which are compatible with DRAM and logic development. This requires that the n-well and p-well design allows for reducing of DRAM storage node array leakage mechanisms for DRAM retention and cell retention, reducing parasitic pnp bipolar current gain, and achieving n-well sheet resistance requirements without impacting p+ MOSFET junction capacitance.
CMOS latchup is a parasitic effect initiated by a parasitic pnp transistor and a parasitic npn transistor forming a parasitic pnpn. Latchup occurs when a large current flows from the pnpn anode to cathode. When a pnpn device triggers, the pnpn undergoes a transition from a low current, high voltage state to a low voltage, high current state. In some cases, the low voltage high current state can lead to thermal runaway and destruction of the elements involved in the formation of the pnpn parasitic element. From a CMOS latchup perspective, the lateral spacings are decreasing, which makes it harder to maintain latchup as CMOS scales. As the technologies scale, the isolation depth is also scaling. The scaling of the isolation also reduces the latchup immunity of the technology. Latchup parasitic gains are a function of well design and p+/n+ spacings. Well profile design, number of implants, doses and energies can significantly vary latchup immunity of a technology. The lateral and vertical profile can influence the parasitic bipolar gain of the lateral and vertical parasitic transistors, respectively. Additionally, latchup is a function of the resistance shunt between the emitter and base of both the pnp and npn transistors. To maintain a low resistance path between the emitter and base of the pnp transistor, high dose implant n-well type retrograde well structures have been used. To maintain a low resistance path between the emitter and base of the npn transistor, high dose implant p-well type retrograde well structures have been used. However, scaling is not maintained because the lateral scaling of dimensions occurs at a faster rate than the vertical scaling dimensions. As a result, significant resistance is established between the well structures and the base substrate and epitaxial wafer as the CMOS technology is scaled even with the existence of retrograde n-well and p-well structures.
In addition to the p-well and n-well structures, a p++ substrate is used to reduce the low resistance path between the emitter and base of the parasitic npn transistor. An epitaxial film is placed on the p++ substrate to form the CMOS devices. From the hot processing, the dopants of the p++ substrate diffuse into the epitaxial region creating an epitaxial flat zone and a smooth dopant transition to the p++ dopant region. This epitaxial film thickness is decreased with continued scaling of CMOS technology. Control of the epitaxial film thickness has become a significant problem in the continuous scaling of the epitaxial film. When the epitaxial film is too thick, the dopants do not diffuse deep enough into the p- epitaxial region, and as a result, the epi resistance is too high and the n-well capacitance significantly decreases. When the epitaxial film is too thin, the p++ dopants compensate the n-well, causing variable n-well sheet resistance. Epitaxial film thickness control leads to being able to maintain the n-well and p-well sheet resistance and capacitance and achieve a process where latchup, SER and ESD objectives are met.
ESD circuit response is also dependent upon epitaxial thickness and n-well design. Epitaxial regions on p+ substrates are scaled in CMOS technology with each technology generation. For technologies with high n-well sheet resistance, scaling the epitaxial thickness will increase the vertical bipolar gain of the vertical pnp formed by the p+ diode, well and p+ substrate. Hence, ESD immunity will improve as the vertical bipolar gain improves. For low n-well sheet-resistance technologies, ESD protection is provided by the diode rather than the vertical bipolar pnp element. Epitaxial scaling degrades ESD protection even though the vertical bipolar gain improves. This is because the ESD immunity is dominated by the ability for the diode to turn-on and discharge to the power rail. As the epitaxial thickness is scaled for a fixed well implant dose, it defines the well depth to first order. Varying the epitaxial thickness modifies the well profile differently than when the well implant dose is increased. In the case of retrograde or low sheet resistance scaled CMOS technology, it has been shown that the lower the resistance, the better the ESD immunity of the process. An important ESD parameter is the "intrinsic temperature". The intrinsic temperature is the temperature at which the intrinsic carrier concentration exceeds the dopant concentration. Increasing the doping concentration increases the intrinsic temperature thereby avoiding thermal runaway. Hence by increasing the dopant concentration in the active regions of the ESD networks, a more ESD immune technology can be created.
"Soft error rate" (SER) from ionizing particles is the result of alpha particles and cosmic rays. Epitaxial thickness and well doping concentration and profiling can influence the diffusion of electron-hole pairs generated by the ionizing radiation. The existence of the p+ wafer improves SER in semiconductor chips. In the epitaxial wafer, in the region where the dopants diffuse into the epitaxial film, the doping concentration is lower and a doping gradient exists. The presence of a lower dopant concentration and the built-in electric field allows for ionized radiation-generated minority carriers to diffuse toward the active circuits near the device surface. Thus it is desirable to provide a solution to reduce the gradient dopant region in the p- epitaxial and p+ substrate region under the n-doped MOSFET diffusions.
MOSFET "snapback" is also a concern in advanced CMOS for burnin voltage stressing and ESD protection. MOSFET snapback occurs when a large voltage is applied to the drain such that avalanche breakdown occurs on the drain-substrate metallurgical junction. The avalanche current initiates a voltage drop between the MOSFET and electrical contacts, leading to the forward biasing of the MOSFET source. The effect causes the transistor to undergo a transition into low voltage, high current state. As the MOSFET channel length scales, the snapback voltage decreases. As a result the maximum applied voltage must be decreased to avoid MOSFET snapback during burnin applications. As the MOSFET scales, without decreasing the epitaxial thickness, MOSFET snapback will not scale with the power supply voltage and channel length. Thus there is a need to provide a solution which is effective to allow proper scaling of the MOSFET snapback with the power supply and channel lengths according to scaling theory.
In the use of tub resistor element applications, n-well resistors are used as in I/O driver design for impedance matching and ESD protection. With a variable epitaxial thickness, due to tolerance, a p++ substrate and retrograde n-well, poor tolerance exists for these circuit elements. There is, therefore, a need to provide a semiconductor construction and method of fabrication which provides good tolerance and control of the n-well sheet resistance for n-wells in a p++ wafer and a thin p-epitaxial film.
Moreover, in tub capacitor elements, n-wells are used as capacitor structures for Vdd capacitance and reduction of noise bounce in dynamic random access memory (DRAM) arrays. The extra Vdd capacitance is useful for both functionality and ESD protection. A variable epitaxial thickness due to tolerance, a p++ substrate and retrograde n-well, poor control is achieved over the n-well capacitance. Accordingly, there is a need to find a semiconductor construction and method of fabrication which provides good tolerance and control of the n-well capacitance for n-wells in a p++ wafer and a thin p- epitaxial film.
Another concern arises with regard to the use of tub breakdown elements. N-wells can charge during manufacturing processing leading to destruction of thin dielectric MOSFET structures. N-wells can also be used as a "floating gate tie-down" to prevent charging of n-channel MOSFET structures. With a variable epitaxial thickness, a p++ substrate and retrograde n-well, poor control is achieved over the n-well breakdown voltage. Accordingly, there is a need to provide a semiconductor construction and method of fabrication which is effective to provide good tolerance and control of the n-well breakdown voltage for n-wells in a p++ wafer and a thin p- epitaxial film.
Another concern is the development of a Zero threshold voltage MOSFET. "Zero VT" MOSFET transistors eliminate the p-well tub and place a standard MOSFET in the native p- epitaxial film. This reduces the threshold voltage of the Zero VT device. Thus the Zero VT device is more prone to leakage and has a lower MOSFET snapback voltage.
A still further concern arises in the context of a manufacturing environment when using the same base wafer for different CMOS technologies. Different device design points are defined such as low power design point, a high performance design point, and a high density design point. In some technologies, two or more objectives may be desirable but not the third. Additionally the same base wafer may be used for different technology generations. For example, 0.5 micron, 0.35 micron and 0.25 micron technology devices may all be currently manufactured in the same fabricator. Using the same wafer base allows for re-adjustment of product mix and generation mix midstream in the semiconductor manufacturing process. In p- wafers and no epitaxial wafers, this is not a concern. However, in p++ wafers with epitaxial films, there is a significant problem in achieving device design goals and using the same p++ wafer and fixed epitaxial film thickness. Thus there is a need to provide a means by which the same epitaxial film thickness and p++ wafers may be used for successive generations of technology scaling development.
P++ buried layers have been implemented into p- wafers to avoid epitaxial growth and to avoid p++ substrate wafers. In such applications, the intent is to avoid the added cost and expense of epitaxial film growth and p++ wafers. In such processes, the usage of the p++ buried implant has the utility of substituting the p++ wafers. There are several problem with that process implementation. First, the resistance using the p++ buried layer is higher than the p++ substrates, so there is no incentive to eliminate the P== substrate. Secondly, in such processes, there exists no denuded zone. This impacts both yield and leakage in VLSI circuits. As a result, the gate oxide integrity (GOI) is inadequate for DRAM development and leakage is inadequate for low power logic applications. Thus there is a need to provide a semiconductor construction and method of fabrication which is effective to address and improve upon these inadequacies.
With specific regard to trench DRAM structures, it is noted that epitaxial variations also influence the trench-gate induced diode leakage (GIDL or TGIDL) mechanism. Trench gate induced diode leakage current has been observed in many substrate plate type trench DRAM cells. Experimental and modeling results show that this is due to electric field-enhanced thermal generation (trap-state barrier lowering and trap-to-band tunneling) at the low electric field regime, and by band-to-band tunneling at the high electric field regime. Since the minority carrier generation is dependent upon the electric fields in the p+ substrate local to the n-well-to-substrate junction, the TGIDL current is influenced by the substrate doping concentration profile. As the epitaxial variation occurs, the trench capacitance of the storage node is modulated. The thicker the epitaxial film, the lower the trench DRAM storage node capacitance. To observe the relationship of increase TGIDL current with electric fields as a function of substrate doping concentration profile, the TGIDL current can be plotted against trench capacitance ratio at 3.4 volts and 0.0 volts trench-to-substrate DC bias. Epitaxial layer design plots of TGIDL current vs n-well breakdown voltage also show that TGIDL current increases with increasing n-well breakdown voltage due to epitaxial variations (n-well breakdown increases linearly with increasing epitaxial thickness in the n-well modulation regime). The increasing TGIDL current with increasing epitaxial thickness constrains the design point due to increasing TGIDL current and decreasing storage node capacitance in shallow collar trench cells. Using a connecting p+ implant layer under the n-well in a substrate plate trench DRAM cell, the doping profile along the trench sidewall prevents the epitaxial modulation of the trench GIDL mechanism. Additionally, as the epitaxial region thickness increases, the depletion region increases along the trench sidewall. The lower the doping concentration, the more leakage occurs along the trench sidewall that is collected at the p++/n-well junction. Accordingly, there is a need to provide a semiconductor construction and method of fabrication which tends to prevent epitaxial variation on the trench GIDL mechanism.